Semiconductor devices constructed using bipolar transistors are inclined to have their base widths formed as thinly as possible in order to achieve high speeds.
FIG. 5 shows a related method of manufacturing a semiconductor device having a bipolar transistor. An embedded n+ layer 12 and an n-epitaxial growth layer 14 are formed on a p-type silicon substrate 10 taken as a semiconductor substrate. A trench element separation insulation film 16 and a field insulation film 18 are formed on the p-type silicon substrate 10. A silicon oxide film 11 is formed on the region forming the trench element separation insulation film 16, the field insulation film 18 and a bipolar transistor and a surface of the p-type silicon substrate 10 is then flattened. A contact hole is then formed at the silicon oxide film 11 on the n-type epitaxial growth layer. A polysilicon film is then formed on the entire surface of the p-type silicon substrate 10 using CVD (Chemical Vapor Deposition) techniques. Predetermined patterns can then be formed from the polysilicon film by subjecting the polysilicon film to photolithographic and etching. After this, impurities are injected into the p-type silicon substrate 10 in the following manner. An n-type impurity is injected into the polysilicon pattern connected to the n-epitaxial growth layer 14. A p-type impurity is then injected at a polysilicon pattern constituting a base lead-out electrode. A prescribed impurity is then injected into a polysilicon pattern constituting a resistance element. The p-type silicon substrate 10 is then heated to a temperature of 900 to 1000.degree. C. A collector n+ layer 20 diffused with n-type impurity is then formed at the n-epitaxial growth layer 14 as a result of this heat treatment. Similarly, a base lead-out electrode 26 and a resistance element 24 having a prescribed resistance value are formed at the silicon oxide film 11 as a result of this heat treatment. This situation is shown in FIG. 5(a).
Next, a silicon oxide film 28 is formed as an insulation film at the surface of the p-type silicon substrate 10. After this, an opening is formed at a prescribed region of the base lead-out electrode 26 using photolithographic and etching processes. Next, a silicon nitride film 30 is formed as an insulation film at the silicon oxide film 28 including the opening. A silicon nitride film side wall is then formed within the opening by etching. The silicon oxide film 11 is then removed from within the opening and a p-type epitaxial layer is formed at the p-type silicon substrate 10. This p-type silicon substrate 10 is then the base p layer 32. This situation is shown in FIG. 5(b).
A polysilicon film including an n-type conductive impurity that becomes an emitter lead-out electrode 36 to be described later is formed on the surface of the silicon nitride film 30. Next, an emitter n+ layer 34 is formed at the p-type silicon substrate 10 using heat treatment. An emitter lead-out electrode 36 is then formed on the p-type silicon substrate 10 using photolithographic and etching processing, so that an npn transistor is formed as a result of the above processes. This situation is shown in FIG. 5(c).
After this, a protective pattern is formed for the silicon oxide film 38a on the resistance element 24. Next, polysilicon film not covered by the polysilicon oxide film 38a is injected with impurity ions. This ion injection is carried out in order to lower the resistance of contacts connecting interconnect formed afterwards and the resistance element. A silicon oxide film 42 is then formed on the surface of the p-type silicon substrate 10 as an insulation film. Next, a contact hole is formed at the silicon oxide film 42 using photolithographic and etching processing. This contact hole is used for electrically connecting the base lead-out electrode 26 emitter lead-out electrode 36, collector lead-out electrode 22 and resistance element 24 to interconnect formed afterwards. An interconnect plug 44 is then formed by burying the contact hole thus formed with a high fusion point metal such as tungsten. An aluminum alloy film constituting an interconnect film is then formed on the silicon oxide film 42 including the interconnect plug 44. Interconnect 46 is then formed by patterning this aluminum alloy film. After this, an insulation film 48 is formed as a protective film on the silicon oxide film 42 including the interconnect 46. This situation is shown in FIG. 5(d).
The width of the base film can therefore be made thin by controlling the thickness of the base p layer 32 and the diffusion of the emitter n+ film 34 in this manner.
However, in the aforementioned semiconductor device manufacturing method there is the fear that the width of the base layer will be formed in an uneven manner due to the p-type epitaxial layer being formed in a thin manner in order to increase speed. This kind of unevenness in the base layer width dramatically influences the amplification factor of the bipolar transistor. In order to suppress this influence, the value of the resistance element 24 required in bias regulation is adjusted in line with the amplification factor of the transistor. As a method of adjustment, there is provided a method where the resistance value of the resistance element 24 is adjusted using the position of a contact for connecting with the resistance element 24. This adjustment of the contact position is carried out by modifying the mask. However, in this method it is necessary to prepare a new mask for adjustment, and the range of adjustment of the resistance value is narrow. Further, the resistance element pattern is formed long beforehand in order to broaden the degree of freedom of setting the position of contact. Parasitic capacitance occurring between the resistance element pattern and the p-type silicon substrate 10 therefore increase and interconnect delays become more substantial.